Packaged integrated circuit devices with through-body conductive vias, and methods of making same

ABSTRACT

A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

BACKGROUND OF THE INVENTION

1. Technical Field

This subject matter disclosed herein is generally directed to the fieldof packaging integrated circuit devices, and, more particularly, topackaged integrated circuit devices with through-body conductive viasand various methods of making same.

2. Description of the Related Art

Integrated circuit technology uses electrical devices, e.g.,transistors, resistors, capacitors, etc., to formulate vast arrays offunctional circuits. The complexity of these circuits requires the useof an ever-increasing number of linked electrical devices so that thecircuit may perform its intended function. As the number of transistorsincreases, the integrated circuitry dimensions shrink. One challenge inthe semiconductor industry is to develop improved methods forelectrically connecting and packaging circuit devices which arefabricated on the same and/or on different wafers or chips. In general,it is desirable in the semiconductor industry to construct transistorswhich occupy less surface area on the silicon chip/die.

In the manufacture of semiconductor device assemblies, a singlesemiconductor die is most commonly incorporated into each sealedpackage. Many different package styles are used, including dual inlinepackages (DIP), zig-zag inline packages (ZIP), small outline J-bends(SOJ), thin small outline packages (TSOP), plastic leaded chip carriers(PLCC), small outline integrated circuits (SOIC), plastic quad flatpacks (PQFP) and interdigitated leadframe (IDF). Some semiconductordevice assemblies are connected to a substrate, such as a circuit board,prior to encapsulation. Manufacturers are under constant pressure toreduce the size of the packaged integrated circuit device and toincrease the packaging density in packaging integrated circuit devices.

In some cases, packaged integrated circuit devices have been stacked ontop of one another in an effort to conserve plot space. Prior arttechniques for conductively coupling the stacked packaged integratedcircuit devices to one another typically involved the formation ofsolder balls or wire bonds to establish this connection. What is desiredis a new and improved technique for conductively coupling stackedpackaged integrated circuit devices to one another.

BRIEF DESCRIPTION OF THE DRAWINGS

The present subject matter may be understood by reference to thefollowing description taken in conjunction with the accompanyingdrawings, in which like reference numerals identify like elements, andin which:

FIG. 1 is a schematic depiction of an illustrative packaged integratedcircuit die with a plurality of conductive through-body vias asdescribed herein;

FIG. 2 is a schematic depiction of an illustrative packaged integratedcircuit comprised of multiple die with a plurality of conductivethrough-body vias as described herein;

FIG. 3 is a schematic cross-sectional view of an illustrative stackedpackaged device disclosed herein;

FIG. 4 is a schematic cross-sectional view of another illustrativestacked packaged device disclosed herein;

FIG. 5 is a schematic cross-sectional view of yet another illustrativestacked packaged device disclosed herein;

FIGS. 6A-6H schematically depict one illustrative method of forming thestacked packaged devices disclosed herein; and

FIGS. 7A-7I schematically depict another illustrative method of formingthe stacked packaged devices disclosed herein.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

Illustrative embodiments of the present subject matter are describedbelow. In the interest of clarity, not all features of an actualimplementation are described in this specification. It will of course beappreciated that in the development of any such actual embodiment,numerous implementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

Although various regions and structures shown in the drawings aredepicted as having very precise, sharp configurations and profiles,those skilled in the art recognize that, in reality, these regions andstructures are not as precise as indicated in the drawings.Additionally, the relative sizes of the various features and dopedregions depicted in the drawings may be exaggerated or reduced ascompared to the size of those features or regions on fabricated devices.Nevertheless, the attached drawings are included to describe and explainillustrative examples of the subject matter disclosed herein.

FIG. 1 depicts one illustrative embodiment of a packaged integratedcircuit device 100 as described herein. The packaged integrated circuitdevice 100 comprises an integrated circuit die 12 having a plurality ofbond pads 14, conductive wiring lines 16 (sometimes referred to as aredistribution layer (RDL)), and at least one conductive interconnection18 (sometimes referred to as conductive vias) that extend through a body20 of encapsulant material, e.g., mold compound material. The conductivevia 18 defines a conductive flow path through the thickness of the body20, i.e., between the front 13 and back 15 of the body 20. Theconductive via 18 and the integrated circuit die 12 may be conductivelycoupled to one another using a variety of known techniques andstructures. In the depicted example, the conductive wiring line 16conductively couples the conductive via 18 to the integrated circuit die12. A plurality of schematically depicted solder balls 24 are formed onthe packaged integrated circuit device 100 in accordance with knownprocessing techniques. The solder balls 24, or other like connections,may be employed to conductively couple the packaged integrated circuitdevice 100 to another structure, e.g., a printed circuit board. In FIG.1, the die 12 is embedded in the body of encapsulant material 20. Asused herein, when it is stated that one or more die 12 are embedded in abody of encapsulant material, it is to be understood that only portionsof the body of the die 12 need to be positioned in the encapsulantmaterial. It is not required that the encapsulant material surround allsides of the body of the die 12, although that configuration may beemployed if needed depending upon the particular application.

FIG. 2 depicts one illustrative embodiment of a packaged integratedcircuit device 200 as described herein. The packaged integrated circuitdevice 200 comprises a plurality of integrated circuit die 12 (two areshown) embedded in a single body 20 of encapsulant material, e.g., moldcompound material. In the illustrative example depicted herein, each ofthe die 12 have the same physical size. However, as will be understoodby those skilled in the art after a complete reading of the presentapplication, the die 12 are not required to be the same physical size,nor do they have to perform the same function. Each of the die 12 shownin FIG. 2 have a plurality of bond pads 14, conductive wiring lines 16(sometimes referred to as a redistribution layer (RDL)), and at leastone conductive interconnection 18 (sometimes referred to as conductivevias) that extend through the body 20 of encapsulant material. Since thedevice 200 comprises a plurality of integrated circuit die 12, it may beconsidered to be a multi-chip module (MCM). As in FIG. 1, a plurality ofschematically depicted solder balls 24 are formed on the packagedintegrated circuit device 200 in accordance with known processingtechniques. The solder balls 24, or other like connections, may beemployed to conductively couple the packaged integrated circuit device200 to another structure, e.g., a printed circuit board.

In the depicted embodiment, each of the conductive vias 18 in FIG. 2extend through the thickness of the body 12. The conductive couplingbetween and among the conductive vias 18 and the embedded integratedcircuit die 12 may b established using any of a variety of knowntechniques and structures. In the example shown in FIG. 2, at least oneof the conductive vias 18 is conductively coupled to one of theintegrated circuit die 12 by one or more wiring lines 16, while anotherof the conductive vias 18 is conductively coupled to the otherintegrated circuit die 12 by one or more wiring lines 16 as well.

As will be recognized by those skilled in the art after a completereading of the present application, the methods and techniques disclosedherein may be applied to virtually any type of integrated circuit devicethat may be formed on the die 12. Additionally, the configuration andlocation of the schematically depicted bond pads 14, the conductivewiring lines 16, and the through-body conductive interconnections 18 mayvary depending upon the particular application.

FIGS. 3-5 are schematic cross-sectional views of a plurality of stackedand packaged integrated circuit devices. In the illustrative exampledepicted in FIG. 3, the stacked package 300 comprises a plurality ofindividual embedded die 10A-10D. In the illustrative example depicted inFIG. 3, only four illustrative individual embedded die 10A-10D aredepicted. As set forth above, it is to be understood that in referringto an embedded die or an individual embedded die, the structure needonly comprise at least one integrated circuit die with a portion of thedie body positioned in the body 20 of encapsulant material. However, aswill be recognized by one skilled in the art after a complete reading ofthe present application, the number of individual embedded die 10 in thestacked package 300 may vary depending upon the particular application,i.e., the number of individual embedded die 10 within such a stack 300may be more or less than the illustrative four depicted in FIG. 3.

Each of the illustrative individual embedded die 10A-10D in FIG. 3comprise an integrated circuit die 12, a plurality of bond pads 14,conductive wiring lines 16 (sometimes referred to as a redistributionlayer (RDL)), a plurality of conductive interconnections 18 (sometimesreferred to as conductive vias) that extend through the body 20 ofencapsulated material. A plurality of conductive structures 22 areprovided between adjacent individual embedded die 10 to provide anelectrically conductive path between the various embedded die 10A-10D. Aplurality of schematically depicted solder balls 24 are formed on thepackaged die 10D in accordance with known processing techniques. Thesolder balls 24, or other like connections, may be employed toconductively couple the stacked package 300 to another structure, e.g.,a printed circuit board.

As will be recognized by those skilled in the art after a completereading of the present application, the methods and techniques disclosedherein may be applied to virtually any type of integrated circuit devicethat may be formed on the die 12 and packaged in a stackedconfiguration. Additionally, the configuration and location of theschematically depicted bond pads 14, conductive interconnections 18 andconductive structures 22 shown in FIG. 3 may vary depending upon theparticular application. In the embodiment depicted in FIG. 3, all of thepackaged die are oriented with the front side 13 of the embedded die 10facing a backside 15 of an adjacent embedded die 10.

FIG. 4 depicts another illustrative embodiment of a stacked packageddevice 400. Similar to the embodiment shown in FIG. 3, the embodiment inFIG. 4 comprises four illustrative individual embedded die 10A-10D. InFIG. 4, the individual embedded die 10A-10D are assembled as groups 10Eand 10F prior to assembling these groups into the structure shown inFIG. 4. The first group 10E comprises the individual embedded die 10Aand 10B, while the second group 10F comprises the individual embeddeddie 10C and 10D. A plurality of conductive interconnections or vias 32extend through the bodies 20 of the plurality of die 10 that comprisethe first group 10E, while a plurality of conductive interconnections orvias 34 extend through the bodies 20 of the plurality of the die 10 thatcomprise the second group 10F.

A plurality of conductive structures 22 provide an electricallyconductive path between the two groups 10E and 10F. The individualembedded die 10 within each group may be secured to one another using anadhesive material 28. Note that, in the illustrative example depicted inFIG. 4, the backside 15 of adjacent embedded die 10 are positionedfacing one another. As will be recognized by those skilled in the artafter a complete reading of the present application, the number ofgroups, e.g., groups 10E and 10F, that may be stacked as depicted inFIG. 4 may vary depending upon the particular application, i.e., more orless than the illustrative two groups depicted in FIG. 4 may beassembled into the final stacked package 400. Similarly, the number ofindividually embedded die 10 within each group may be greater than theillustrative two depicted in the groups 10 e and 10F in FIG. 4.

The structures depicted in FIGS. 3 and 4 may be combined if desired. Forexample, FIG. 5 depicts an illustrative stacked packaged device 500wherein the bottom two embedded die 10A-10B are packaged as a group 10E,while the upper two embedded die 10C-10D are packaged as depicted inFIG. 3. Thus, it is readily apparent that the methodologies and devicesdisclosed herein provide great flexibility as it relates to creatingstacked packaged devices to thereby reduce plot space consumption andimprove packaging densities. Moreover, in FIGS. 3-5, each of theindividual embedded die 10 are depicted as having a single integratedcircuit die 12 embedded therein. In accordance with one aspect of thepresent disclosure, the individual embedded die 10 may comprise aplurality of individual integrated circuit die 12, like the multi-chipembodiment depicted in FIG. 2. That is, the methods and devicesdisclosed herein may be employed with individual embedded die 10 thatcomprise single or multiple integrated circuit die 12. For ease ofreference, the following description will make reference to anindividual embedded die 10 comprised of a single integrated circuit die12, although the methods may readily be applied to embedding a pluralityof integrated circuit die 12 in a single body 20 of encapsulant materialof an individual embedded die.

FIGS. 6A-6H depict one illustrative method of forming the devicesdisclosed herein. In FIG. 6A, a plurality of known good integratedcircuit die 12 are placed front side 13 down above an illustrativesacrificial structure 30. In one illustrative example, the sacrificialstructure 30 may be a film frame with dicing tape positioned across thefilm frame. The structure 30 is sacrificial in the sense that it willlater be removed. In FIG. 6B, a body 20 of encapsulant material, e.g.,mold compound, is formed around the integrated circuit die 12 and abovethe structure 30, i.e., the integrated circuit die 12 is embedded in thebody 20. Traditional molding techniques, e.g., injection molding, may beperformed to form the body 20 of encapsulant material. Thereafter, asshown in FIG. 6C, the sacrificial structure 30 may be removed. In theillustrative example described herein, the structure 30 may simply bepeeled away due to the use of the adhesive tape as part of the structure30.

Next, as shown in FIG. 6D, the conductive lines 16 are formed above thefront side 13 of the integrated circuit die 12 and body 12 in accordancewith traditional techniques. Of course, the conductive lines 16 may haveany desired configuration and they may be made from any desiredmaterial. Then, as indicated in FIG. 6E, a plurality of openings or vias17 are formed through the body 20 as indicated. The openings 17 may beformed by a variety of known techniques, e.g., laser drilling, etchingetc. In some applications, a masking layer (not shown) may be formed aspart of the process of forming the openings 17. The openings 17 may beof any desired shape or configuration. Note that, in the illustrativeexample depicted herein, the openings 17 are formed from the backside 15toward the front side 13 of the body 20 of the embedded die 10. Alsonote that, in this particular example, the openings 17 expose, but donot extend through, the conductive interconnections 16 formed on thefront side 13 of the embedded die 10. Thereafter, as shown FIG. 6F, theopenings 17 are filled with a conductive material, e.g., copper,aluminum, silver, etc., to form the conductive interconnections 18. Theconductive material may be formed in the openings 17 using any of avariety of known techniques, e.g., plating, deposition, etc., and avariety of different conductive materials may be employed, dependingupon the particular application.

In FIG. 6G, a plurality of conductive structures 22 are formed on theembedded die 10A-10B using known techniques. In some cases, theconductive structures 22 may be formed as part of the process of formingthe conductive interconnections 18. Then, as shown in FIG. 6H, a dicingor singulating process is performed along cut line 37 to produce theillustrative individual embedded die 10A and 10B.

Next, the individual embedded die 10A-10B are subject to a variety oftests to confirm their acceptability for their intended application.Once the embedded die 10A-10B have successfully passed such tests, theyare ready to be shipped to customers. In other applications, the testedembedded die 10A-10B may be assembled into a stacked packaged device300, 400, 500 as depicted herein. In the example depicted in FIG. 3, aplurality of individual embedded die 10 are positioned as depicted inFIG. 3 and a reflow process is performed to establish the electricalconnection between the conductive structures 22 on an individualembedded die, e.g., die 10A, and the conductive interconnections 18 onan adjacent embedded die, e.g., die 10B. The illustrative solder balls24 may be formed on the illustrative die 10 using traditionaltechniques. The solder balls 24 may be formed at any desired pointduring the process flow. For example, the solder balls 24 may be formedafter all of the embedded die 10A-10D are assembled as depicted in FIG.3. Alternatively, the solder balls 24 may be formed above the individualembedded die 10D prior to assembling the individual embedded die 10Dwith the other individual embedded die as depicted in FIG. 3.

FIGS. 7A-7I depict another illustrative method of forming the devicesdisclosed herein. The steps depicted in FIGS. 7A-7D are the same asthose previously described with respect to FIGS. 6A-6D. Thus, a detaileddiscussion of FIGS. 7A-7D will not be repeated. In FIG. 7E, a pluralityof the structures depicted in FIG. 7D are secured to one another usingan adhesive material 28. Thereafter, in FIG. 7F, a plurality of openingsor vias 31 are formed through the bodies 20 of the combined structuredepicted in FIG. 7E. The openings 31 may be formed by a variety of knowntechniques, e.g., laser drilling, etching etc. In some applications, amasking layer (not shown) may be formed as part of the process offorming the openings 31. The openings 31 may be of any desired shape orconfiguration. Note that, in the illustrative example depicted herein,the openings 31 extend through the conductive interconnections 16 formedon the front side 13 of each of the individual structures. Thereafter,as shown FIG. 7G, the openings 31 are filled with a conductive material,e.g., copper, aluminum, silver, etc., to form the through bodyconductive vias 32. The conductive material may be formed in theopenings 31 using any of a variety of known techniques, e.g., plating,deposition, etc., and a variety of different conductive materials may beemployed, depending upon the particular application.

In FIG. 7H, a plurality of conductive structures 22 are formed on thestructure depicted in FIG. 7G using known techniques. In some cases, theconductive structures 22 may be formed as part of the process of formingthe conductive interconnections 32. Next, as shown in FIG. 7I, a dicingor singulating process is performed along cut line 37 to produce theillustrative groups 10E and 10F of the individual embedded die.

Next, the groups of embedded die 10E-10F are subject to a variety oftests to confirm their acceptability for their intended application.Once the groups 10E-10F have successfully passed such tests, they areready to be shipped to a customer. In some applications, the groups ofembedded die 10E-10F may be assembled into a stacked packaged device asdescribed herein. In the example depicted in FIG. 4, the groups ofembedded die 10E and 10F are positioned as depicted in FIG. 4 and areflow process is performed to establish the electrical connectionbetween the conductive structures 22 on the first group 10E and theconductive vias 32 on an adjacent group 10F. The illustrative solderballs 24 may be formed on an illustrative individual embedded die in thegroup 10F using traditional techniques. The solder balls 24 may beformed at any desired point during the process flow. For example, thesolder balls 24 may be formed after the two illustrative groups 10E-10Fare assembled as depicted in FIG. 4. Alternatively, the solder balls 24may be formed above one of the individual embedded die in the group 10Fprior to assembling the two groups together as depicted in FIG. 4.

As will be recognized by those skilled in the art after a completereading of the present application, the present disclosure may providevery efficient means for packaging individual die and providing stackedpackaged integrated circuit devices. Much of the processing performedherein may be performed on multiple die at a single time as opposed toperforming such operations on individual die one at a time. For example,although two illustrative die 12 are depicted in FIGS. 6A-6H and 7A-7I,the processing steps described herein may be performed on any desirednumber of die, depending upon the processing capability of theprocessing tools employed. In short, wafer level processing techniquesmay be employed to increase the efficiency of packaging operations,i.e., the processing operations may be performed on multiple die at thesame time.

1. A device, comprising: at least one integrated circuit die, at least aportion of which is positioned in a body of encapsulant material; and atleast one conductive via extending through the body of encapsulantmaterial.
 2. The device of claim 1, wherein the device comprises aplurality of individual integrated circuit die, each of which have aportion which is positioned in the body of encapsulant material.
 3. Thedevice of claim 2, wherein the device comprises a plurality of theconductive vias that extend through the body of encapsulant material,and wherein at least one of the conductive vias is conductively coupledto one of the plurality of integrated circuit die and another of theconductive vias is conductively coupled to another of the plurality ofintegrated circuit die.
 4. The device of claim 1, wherein the at leastone conductive via is conductively coupled to the at least oneintegrated circuit die by a conductive wiring line.
 5. The device ofclaim 1, wherein the at least one conductive via extends through athickness of the body of encapsulant material.
 6. The device of claim 1,wherein the at least one conductive via defines a conductive flow pathbetween a front side and a back side of the body of encapsulantmaterial.
 7. A device, comprising: a plurality of integrated circuitdie, each of which is embedded in a single body of encapsulant material;and a plurality of conductive vias extending through the body ofencapsulant material.
 8. The device of claim 7, wherein at least one ofthe conductive vias is conductively coupled to one of the plurality ofintegrated circuit die and another of the conductive vias isconductively coupled to another of the plurality of integrated circuitdie.
 9. The device of claim 8, wherein the conductive vias areconductively coupled to the respective integrated circuit die by aconductive wiring line.
 10. The device of claim 7, wherein the pluralityof conductive vias extend through a thickness of the single body ofencapsulant material.
 11. The device of claim 7, wherein the pluralityof conductive vias define a plurality of conductive flow paths between afront side and a back side of the single body of encapsulant material.12. The device of claim 7, wherein each of said plurality of die havethe same physical size.
 13. A device, comprising: a plurality ofindividual embedded die, each of the individual embedded die comprisinga body of encapsulant material and at least one conductive via extendingthrough the body of encapsulant material, the plurality of embedded diebeing positioned adjacent one another; and at least one conductivestructure positioned between adjacent individual embedded die, theconductive structure providing an electrically conductive path betweenconductive vias in adjacent individual embedded die.
 14. The device ofclaim 13, wherein the conductive via extends through a thickness of thebody of encapsulant material.
 15. The device of claim 13, wherein atleast one of the plurality of individual embedded die comprises a singleintegrated circuit die.
 16. The device of claim 13, wherein at least oneof the plurality of individual embedded die comprises a plurality ofintegrated circuit die.
 17. The device of claim 13, wherein theplurality of individual embedded die are stacked vertically above oneanother.
 18. The device of claim 17, wherein the plurality of individualembedded die are positioned such that a front side of one of theindividual embedded die faces a back side of an adjacent individualembedded die.
 19. A device, comprising: a first and a second embeddeddie, each of the first and second embedded die comprising a body ofencapsulant material, a back side of each of the first and secondembedded die being positioned facing one another; and a conductive viathat extends through the body of encapsulant material of both the firstand second embedded die.
 20. The device of claim 19, wherein theconductive via extends from a front side of the first embedded die to afront side of the second embedded die.
 21. The device of claim 19,further comprising an adhesive material positioned between the backsides of the first and second embedded die for securing the first andsecond embedded die to one another.
 22. The device of claim 21, whereinthe first and second embedded die are stacked vertically above oneanother.
 23. A device, comprising: a first group of embedded die and asecond group of embedded die, each of the first and second groups ofembedded die comprising a plurality of individual embedded die, each ofthe individual embedded die comprising a body of encapsulant material;at least one first conductive via that extends through the first groupof embedded die; at least one second conductive via that extends throughthe second group of embedded die; and at least one conductive structurepositioned between the first and second groups of embedded die thatprovides an electrically conductive flow path between the first andsecond conductive vias.
 24. The device of claim 23, wherein a back sideof each of the individual embedded die in each of the first and secondgroups of embedded die are positioned facing one another.
 25. The deviceof claim 24, wherein the first conductive via extends from a front sideof an individual embedded die in the first group of embedded die to afront side of another individual embedded die in the first group ofembedded die.
 26. The device of claim 24, further comprising an adhesivematerial positioned between the facing back sides of the individualembedded die.
 27. The device of claim 23, wherein the first conductivevia is formed through the body of encapsulant material of all of theindividual embedded die in the first group of embedded die.
 28. Thedevice of claim 27, wherein the second conductive via is formed throughthe body of encapsulant material of all of the individual embedded diein the second group of embedded die.
 29. The device of claim 23, whereineach of the individual embedded die comprises a single integratedcircuit die.
 30. The device of claim 23, wherein each of the individualembedded die comprises a plurality of integrated circuit die.
 31. Thedevice of claim 23, wherein the first and second groups of embedded dieare stacked vertically above one another.
 32. A method, comprising:forming a body of encapsulant material around at least a portion of atleast one integrated circuit die; forming at least one conductive viathat extends through the body of encapsulant material; and conductivelycoupling the at least one conductive via to the at least one integratedcircuit die.
 33. The method of claim 32, wherein forming the conductivevia comprises forming an opening in the body of encapsulant material andfilling the opening with a conductive material.
 34. The method of claim32, wherein conductively coupling the at least one conductive via to theat least one integrated circuit die comprises forming at least oneconductive wiring line that is connected to the at least one conductivevia and the at least one integrated circuit.
 35. The method of claim 32,wherein forming the body of encapsulant material comprises performing aninjection molding process to form the body of encapsulant material. 36.The method of claim 32, wherein forming the body of encapsulant materialcomprises forming the body of encapsulant material around a plurality ofindividual integrated circuit die.
 37. The method of claim 36, furthercomprising performing a singulating process to define a plurality ofindividual embedded die, each of which are comprised of a singleintegrated circuit die.
 38. The method of claim 37, further comprising:positioning a plurality of the individual embedded die adjacent oneanother; and conductively coupling the conductive via on a first of theindividual embedded die to the conductive via on a second of theindividual embedded die.
 39. The method of claim 38, wherein theplurality of the individual embedded die are positioned such that afront surface of a first individual embedded die faces a back side of anadjacent individual embedded die.
 40. The method of claim 38, whereinconductively coupling the conductive vias on the first and secondindividual embedded die comprises forming a conductive structure betweenthe first and second individual embedded die.
 41. The method of claim39, further comprising stacking the second individual embedded die abovethe first individual embedded die.
 42. The method of claim 36, furthercomprising performing a singulating process to define a plurality ofindividual embedded die, each of which are comprised of a plurality ofintegrated circuit die.
 43. The method of claim 42, further comprising:positioning a plurality of the individual embedded die adjacent oneanother; and conductively coupling the conductive via on a first of theindividual embedded die to the conductive via on a second of theindividual embedded die.
 44. The method of claim 43, wherein theplurality of individual embedded die are positioned such that a firstsurface of a first individual embedded die faces a back side of anadjacent individual embedded die.
 45. The method of claim 43, whereinconductively coupling the conductive vias on the first and secondindividual embedded die comprises forming a conductive structure betweenthe first and second individual embedded die.
 46. The method of claim45, further comprising stacking the second individual embedded die abovethe first individual embedded die.
 47. A method, comprising: positioninga first individual embedded die adjacent a second individual embeddeddie, each of the first and second individual embedded die comprising abody of encapsulant material; and forming at least one conductive viathat extends through the body of encapsulant material of both of thefirst and second individual embedded die.
 48. The method of claim 47,further comprising conductively coupling the at least one conductive viato at least one integrated circuit die in one of the first and secondindividual embedded die.
 49. The method of claim 47, wherein at leastone of the first and second individual embedded die comprises a singleintegrated circuit die.
 50. The method of claim 47, wherein at least oneof the first and second individual embedded die comprises a plurality ofintegrated circuit die.
 51. The method of claim 47, further comprisingsecuring the first and second individual embedded die to one anotherprior to forming the at least one conductive via.
 52. The method ofclaim 51, wherein securing the first and second individual embedded dieto one another comprises applying an adhesive material to at least oneof the first and second individual embedded die.
 53. The method of claim47, wherein the first and second individual embedded die are positionedsuch that a back side of the first individual embedded die faces a backside of the second individual embedded die.